(单选题)17: 在VHDL语言中,下列对时钟边沿检测描述中,错误的是
A: if clk’event and clk = ‘1’ then
B: if falling_edge(clk) then
C: if clk’event and clk = ‘0’ then
D: if clk’stable and not clk = ‘1’ then
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